Smart Ways to Catch the Abutment DRCs at IP Level

Abstract

While developing any IP layout internal DRCs (Design Rule Check) will be taken care of with the help of Foundry decks. But it will be important to catch the DRCs when such IPs sit next to each other. Such DRCs are called Abutment/Half DRCs. These DRCs must be clean, or else during the Placement and Route(PnR) stage of the Design, SOC designers will see surprising DRC errors, even though the cells were individually DRC clean. These DRCs must be caught early in the design stage. Otherwise, errors seen during Vt change/ECO change will cause delay on the Tape-out schedule and/or area penalty. Current innovation highlights Smart ways to catch such Abutment DRCs at the IP level. The main target is Standard cell IPs, but the idea can easily be ported to any other IPs.