Design and FPGA Realization of Energy Efficient Reversible Full Adder for Digital Computing Applications

Abstract

Arithmetic  primitives   are  necessary   in  order   to  conduct   computations  on  large  numbers  in  arithmetic  circuit implementations including  multiplications, additions,  subtractions, and  divisions.  Because of the importance of computations in the central processing unit, effective design of arithmetic circuit has been part of the most important fields of research for design engineers.  In order  to create  low-power and  energy-efficient portable  processors  for image and  digital  signal processing, as well as cryptography  applications, the  switching  activity  factor  and  cell count  must  be reduced. This  research focuses on the  reversible digital  full adder  circuit,  which  is a  key element  in establishing  the  Energy  Delay Product (EDP)  for  various computer applications. Here, a new reversible binary full adder is designed using the switching activity concept and the logic decomposition method.  The  internal  blocks for  reversible full adders  such  as Feynman  Gate,  Toffoli Gate,  and  New Gate  are designed  first,  then  a  new  reversible binary  full  adder  is developed  using  the  proposed  method.  In  this  paper,  conventional and  proposed  reversible full adders  are  synthesized  using  the  Xilinx Vivado  design  suite  for  the  Zynq-7000  family  of device configuration.   According  to  the  implementation  results,  the  proposed   reversible  full  adder   circuit   consumes  less  dynamic power  dissipation   than  the  existing  method  in  comparison.   Furthermore, a formulae-based evaluation   is conducted   on the implementation results to estimate the EDP of the design. The proposed reversible full adder design can achieve a 32.3% EDP improvement compared to the Proposed Full Adder.