Machine Learning Dependent Arithmetic Module Realization for High-Speed Computing

Authors

  • Cedomir Marangunic
  • Felipe Cid
  • Andrés Rivera
  • José Uribe

DOI:

https://doi.org/10.31838/jvcs/04.01.07

Keywords:

8-bit ALU, EDP, FinFET, Full Adder, GDI, PDP, Static leakage current.

Abstract

Since last few years, the tiny size of MOSFET, that is less than tens of nanometers, created some operational problems such as increased gate-oxide leakage, amplified junction leakage, high sub-threshold conduction, and reduced output resistance. To overcome the above challenges, FinFET has the advantages of an increase in the operating speed, reduced power consumption, decreased static leakage current is used to realize the majority of the applications by replacing MOSFET. By considering the attractive features of the FinFET, an ALU is designed as an application. In the digital processor, the arithmetic and logical operations are executed using the Arithmetic logic unit (ALU). In this paper, power efficient 8-bit ALU is designed with Full adder (FA) and multiplexers composed of Gate diffusion input (GDI) which gained designer’s choice for digital combinational circuit realization at minimum power consumption.
The design is simulated using Cadence virtuoso with 20nm technology. Comparative performance analysis is carried out in contrast to the other standard circuits by taking the critical performance metrics such as delay, power, and power delay product (PDP), energy-delay product (EDP) metrics into consideration.

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Published

2022-09-28

How to Cite

Cedomir Marangunic, Felipe Cid, Andrés Rivera, & José Uribe. (2022). Machine Learning Dependent Arithmetic Module Realization for High-Speed Computing. Journal of VLSI Circuits and Systems, 4(01), 42–51. https://doi.org/10.31838/jvcs/04.01.07

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Articles