Vol. 4 No. 01 (2022): JVCS

Articles

• An Innovative Design of Decoder Circuit using Reversible Logic

  G V Vinod, D Vijendra Kumar, N M Ramalingeswararao

  1-6

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• An Improved Design of Low-Power High-Speed Accuracy Scalable Approximate Multiplier

  Jagadeesh Bodapati, Oggi Sudahkar, Atava G V Karthik Raju

  7-11

  • pdf

• Implementation of Fundamental Modules Using Quantum Dot Cellular Automata

  Vallabhuni Vijay, Chandra S. Pittala, A. Usha Rani, Sadulla Shaik, M.V.Saranya, B. Vinod Kumar, R.E.S Praveen Kumar, Rajeev R. Vallabhuni

  12-19

  • pdf

• Design of Unbalanced Ternary Logic Gates and Arithmetic Circuits

  Vallabhuni Vijay, Chandra S. Pittala, K. C. Koteshwaramma, A. Sadulla Shaik, Kancharapu Chaitanya, Shiva G. Birru, Soma R. Medapalli, Varun R. Thoranala

  20-26

  • pdf

• A Review On N-Bit Ripple-Carry Adder, Carry-Select Adder And Carry-Skip Adder

  Vallabhuni Vijay, M. Sreevani, E. Mani Rekha, K. Moses, Chandra S. Pittala, K. A. Sadulla Shaik, C. Koteshwaramma, R. Jashwanth Sai, Rajeev R. Vallabhuni

  27-32

  • pdf

• Physically Unclonable Functions Using Two-Level Finite State Machine

  Vallabhuni Vijay, Kancharapu Chaitanya, Chandra Shaker Pittala, Ajitha. G, S. Susri Susmitha, J. Tanusha, S. China Venkateshwarlu, Rajeev Ratna Vallabhuni

  33-41

  • pdf

• Machine Learning Dependent Arithmetic Module Realization for High-Speed Computing

  Cedomir Marangunic, Felipe Cid, Andrés Rivera, José Uribe

  42-51

  • pdf

• Ultra Low Potential Operated Fundamental Arithmetic Module Design for High-Throughput Applications

  O.J.M. Smith, F. de Mendonça, K.N. Kantor, A. A. Zaky, G.F. Freire

  52-59

  • pdf