Vol. 5 No. 01 (2023): JVCS

Articles

• Fundamental Flip-Flop Design: Comparative Analysis

  Kagaba J. Bosco, S. M Pavalam, L.J. Mpamije

  1-7

  • pdf

• Data Conversion: Realization of Code converter using Shift Register Modules

  Blessing Kabasa, Edward Chikuni, M.P. Bates, T.G. Zengeni

  8-19

  • pdf

• Flip-Flop Realization: Conventional Memory Elements Design with Transistor Nodes

  Andrew Muyanja, Peter Nabende, J. Okunzi, Mark Kagarura

  20-27

  • pdf

• Multiplier Design using Machine Learning Alogorithms for Energy Efficiency

  Jane Juma, R.M. Mdodo, David Gichoya

  28-34

  • pdf

• Memory Module: High-Speed Low Latency Data Storing Modules

  Doris Klein, Stefan Dech, Bradley Raddwine, Ernst Uken

  35-41

  • pdf

• CMOS Technology: Conventional Module Design for Faster Data Computations

  Fasil Beyene, Kinfe Negash, Getahun Semeon, Besufekad Getachew

  42-48

  • pdf

• Data Distinguisher Module Implementation using CMOS Techniques

  M.R. Usikalu, E. N. C. Okafor, D. Alabi, G. N. Ezeh

  49-54

  • pdf

• Fundamental Design Approach: Realization of Decoder Block for Secured Transmission

  Fahad Al-Jame, Rana A. Al-Fares, Wesam Ali, H. Ashour, Nimer Murshid

  55-60

  • pdf

• Physical Design of Speed Improvised Factor in FPGA Applications

  Mohamed Atef Abbas, Tarek M. Hatem, Mohamed A. Tolba, M. Atia

  61-66

  • pdf