Vol. 7 No. 1 (2025): Current issue

Published: 2025-01-20

Articles

Impact of Digital Technologies on Economic and Marketing Innovation and Competitiveness within VLSI System Employment

Solomiya Ohinok, Ihor Kulyniak, Maryana Kohut, Iryna Gerlach, Oksana Voronko

1-10
- PDF
Design and Optimization of Coarse-Grained Reconfigurable Array (CGRA) Architecture for Efficient Processing-in-Memory (PIM) Systems

Anas A. Salameh, Kho Mei Ye

11-18
- PDF
Adaptive VLSI Design Using Dynamic Voltage and Frequency Scaling (DVFS) for Low-Latency IoT Communication Networks

Anas A. Salameh, Faizal Baharum

19-25
- PDF
Design of a optimized CMOS Differential Amplifier using Craziness-based PSO

Sandeep Kumar Dash, Bishnu Prasad De, Bhargav Appasani, Nirmal Kumar Rout, Avireni Srinivasulu

26-31
- PDF
Efficient Design of Up Sampler and Down Sampler using Single Electron Transistor-Metal Oxide Semiconductor Field Effect Transistor

Shobhika Gopnarayan, Shriram Markande

32-39
- PDF
Design of a 64-bit SQRT-CSLA with Reduced Area and High-Speed Applications in Low Power VLSI Circuits

CH. Pallavi, C. Padma, R. Kiran Kumar, T. Suguna, C. Nalini

40-45
- PDF
Automated Compliance Systems in International Trade: The Role of AI and VLSI Systems in Streamlining Customs Procedures

Marta Sarvas, Yuliya Bondarenko, Liliya Ukraynets, Pavlo Sorokovyi, Ivan Zhygalo

46-55
- PDF
High Speed Energy Efficient Latch Architectures for Sequential Circuit Design

Renu Kumawat, Tripti Dua , Neha Singh, Jyoti Sharma, Avireni Srinivasulu

56-65
- PDF
Efficient VLSI Architecture Integrating Vedic Mathematics for Square Computation

U. G. Patil, Prabodh Jagtap, Kedar Adake, Sanika Dhanbhar, Ajay Paithane

66-74
- PDF
A 3.7-4.8GHz Programmable Integer-N PLL With Multi-Modulus Divider and Tunable VCO in Standard 45nm CMOS Technology

Dr. Garima Kapur

75-82
- PDF
VLSI Systems as the Engine for the Knowledge Society: Enabling Information Culture through Technological Innovation

Mykhailo Poplavskyi , Oksana Oliinyk , Yurii Horban

83-93
- PDF
Energy-Efficient GNRFET-Based Ternary Full Adder for Next-Generation Integrated Circuits

J. Pradeep, R. Bhavithra

94-105
- PDF
DFT Aware Test Architecture for Communication ICs: ATPG- Based Fault Detection on Lower Technology Node

Supriya B K , Arunraja A, Bremiga Gopalan Gandhimathi, S Sheeba Rani, N Sudhakar Reddy, Deepali Rani Sahoo

106-117
- PDF
VLSI-Optimized Post-Quantum Cryptographic Architecture for Secure IoT and Blockchain Applications

Venkatachalam K, Balamanikandan A , Shaik Rahamtula , Karthikayen A , Janardhan Saikumar P , Venkatesan M

118-130
- PDF
Learning-Based Ultra-Low-Power Optimization for VLSI Architectures

Prasanta Panda, Aruna Tripathy, Kanhu Charan Bhuyan

131-144
- PDF

Vol. 7 No. 1 (2025): Current issue

Articles

Impact of Digital Technologies on Economic and Marketing Innovation and Competitiveness within VLSI System Employment

Design and Optimization of Coarse-Grained Reconfigurable Array (CGRA) Architecture for Efficient Processing-in-Memory (PIM) Systems

Adaptive VLSI Design Using Dynamic Voltage and Frequency Scaling (DVFS) for Low-Latency IoT Communication Networks

Design of a optimized CMOS Differential Amplifier using Craziness-based PSO

Efficient Design of Up Sampler and Down Sampler using Single Electron Transistor-Metal Oxide Semiconductor Field Effect Transistor

Design of a 64-bit SQRT-CSLA with Reduced Area and High-Speed Applications in Low Power VLSI Circuits

Automated Compliance Systems in International Trade: The Role of AI and VLSI Systems in Streamlining Customs Procedures

High Speed Energy Efficient Latch Architectures for Sequential Circuit Design

Efficient VLSI Architecture Integrating Vedic Mathematics for Square Computation

A 3.7-4.8GHz Programmable Integer-N PLL With Multi-Modulus Divider and Tunable VCO in Standard 45nm CMOS Technology

VLSI Systems as the Engine for the Knowledge Society: Enabling Information Culture through Technological Innovation

Energy-Efficient GNRFET-Based Ternary Full Adder for Next-Generation Integrated Circuits

DFT Aware Test Architecture for Communication ICs: ATPG- Based Fault Detection on Lower Technology Node

VLSI-Optimized Post-Quantum Cryptographic Architecture for Secure IoT and Blockchain Applications

Learning-Based Ultra-Low-Power Optimization for VLSI Architectures

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